Integrated circuits (ICs), used in many programmable devices, include a variety of input/output (I/O) pins. Some of the I/O pins are used to perform different functions in a user design while others are used as pre-defined test pins. For applications that do not require a high number of I/O pins, some of the unused I/O pins must still exist in the design simply because they are predefined as test pins. These designated I/O test pins are used to test different parts of the IC.
For devices that share the same base layer, it may not be possible to use different packaging configurations simply because some of the I/O pins that are not used in the user application are still needed as test pins. Hence, the test pins generally need to be relocated for every different packaging configuration. This is a cumbersome process as some of the I/O pins may need to be rerouted in order to accommodate different applications and different packaging configurations.
Even though some smaller applications may not require a high number of I/Os, the same packaging configuration might still be needed in order to maintain a certain level of test coverage on the device. In other words, although some applications may require less I/O pins, the device might still have more I/O pins than needed because some I/O pins have already been predefined as test pins. When I/O pins are not assigned specifically to any logic blocks in the device, any existing I/O pins on the device can be used as test pins. This is more flexible than having predefined test pins because it eliminates the need to have specific I/O pins to be routed to specific logic blocks or test circuitry within the device.
Therefore, it is desirable to have configurable test pins that can easily be routed to different parts of the device. It is also desirable to have techniques to easily route the I/O pins so that the same I/O pin can be used as a user I/O pin, an input test pin or an output test pin when required. It is within this context that the invention arises.